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[Other] [Tech Class] Chapter 74: All About DDR Memory

2019-03-05 08:49:44
18360 137

Hello Mi Fans,
Welcome back to Mi Community Tech Class Session. In the previous Tech Class, you got all the information about the Wi-Fi 6. In today's Tech Class, you will learn about DDR Memory.

Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate synchronous dynamic random-access memory class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, and DDR4 memory modules will not work in DDR1-equipped motherboards, and vice versa.

Single generic DDR memory module

Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to double data bus bandwidth without a corresponding increase in clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of an SDR SDRAM running at the same clock frequency, due to this double pumping.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate (in bytes/s) of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

"Beginning in 1996 and concluding in June 2000, JEDEC developed the DDR (Double Data Rate) SDRAM specification (JESD79)." JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules.

Specification standards
Chips and modules
Standard
name
DRAM cell array
clock
(MHz)
Cycle
time
(ns)
I/O bus
clock
(MHz)
Data
rate
(MT/s)
VDDQ
(V)
Module
name
Peak transfer
rate
(MB/s)
Timings
(CL-tRCD-
tRP)
DDR-200100101002002.5±0.2PC-16001600
DDR-266133.337.5133.33266.672.5±0.2PC-21002133.332.5-3-3
DDR-333166.676166.67333.332.5±0.2PC-27002666.67
DDR-400A
DDR-400B
DDR-400C
20052004002.6±0.1PC-320032002.5-3-3
3-3-3
3-4-4

All above listed are specified by JEDEC as JESD79F. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using tighter-tolerance or overvolted chips.


4 DDR slots

The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM designed for different clock frequencies, for example, PC-1600, designed to run at 100 MHz, and PC-2100, designed to run at 133 MHz. The number simply designates the data rate at which the chip is guaranteed to perform, hence DDR SDRAM is guaranteed to run at lower (underclocking) and can possibly run at higher (overclocking) clock rates than those for which it was made.

DDR SDRAM modules for desktop computers, dual in-line memory modules (DIMMs), have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. Most DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 V.

Corsair DDR-400 memory with heat spreaders

JEDEC Standard No. 21–C defines three possible operating voltages for 184 pin DDR, as identified by the key notch position relative to its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD (right), while page 4.20.5–40 nominates 3.3V for the right notch position. The orientation of the module for determining the key notch position is with 52 contact positions to the left and 40 contact positions to the right.

Increasing operating voltage slightly can increase maximum speed, at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage.

Many new chipsets use these memory types in multi-channel configurations.

Physical DDR layout
Chip characteristics
  • DRAM density: Size of the chip is measured in megabits. Most motherboards recognize only 1 GB modules if they contain 64M×8 chips (low density). If 128M×4 (high density) 1 GB modules are used, they most likely will not work. The JEDEC standard allows 128M×4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply.
  • Organization: The notation like 64M×4 means that the memory matrix has 64 million (the product of banks x rows x columns) 4-bit storage locations. There are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC in server environments, while the ×8 and ×16 chips are somewhat less expensive. x8 chips are mainly used in desktops/notebooks but are making entry into the server market. There are normally 4 banks and only one row can be active in each bank.

Module characteristics
  • Ranks: To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with the common address lines are called a memory rank. The term was introduced to avoid confusion with chip internal rows and banks. A memory module may bear more than one rank. The term sides would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address + data). The Chip Select signal is used to issue commands to a specific rank. Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck, new chipsets employ the multi-channel architecture.
  • Capacity
  • Number of DRAM devices: The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximal number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.
  • ECC vs non-ECC: Modules that have error-correcting code are labeled as ECC. Modules without error correcting code are labeled non-ECC.
  • Timings: CAS latency (CL), clock cycle time (tCK), row cycle time (tRC), refresh row cycle time (tRFC), row active time (tRAS).
  • Buffering: registered (or buffered) vs unbuffered.
  • Packaging: Typically DIMM or SO-DIMM.
  • Power consumption: A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the order of 1–3 W per 512 MB module; this increases with a clock rate and when in use rather than idling. A manufacturer has produced calculators to estimate the power used by various types of RAM.

Module and chip characteristics are inherently linked.

Comparison of memory modules for portable/mobile PCs (SO-DIMM).

Total module capacity is a product of one chip's capacity and the number of chips. ECC modules multiply it by 8/9 because they use 1 bit per byte (8 bits) for error correction. A module of any particular size can, therefore, be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip and number of chips. It also equals the number of ranks (rows) multiplied by DDR memory bus width. Consequently, a module with a greater number of chips or using ×8 chips instead of ×4 will have more ranks.

Example: Variations of 1 GB PC2100 registered DDR SDRAM module with ECC
Module size (GB)Number of chipsChip size (Mbit)Chip organizationNumber of ranks
13625664Mx42
11851264Mx82
118512128Mx41

This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single- or dual-ranked.

There is a common belief that the number of module ranks equals the number of sides. As the above data shows, this is not true. One can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it's unlikely such a module was ever produced.

History
Double data rate (DDR) SDRAM specification
From Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametric.

Standard No. 79 Revision Log:
  • Release 1, June 2000
  • Release 2, May 2002
  • Release C, March 2003 – JEDEC Standard No. 79C.

"This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametric, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well."

Organization
PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with 16 512 Mbit chips, 8 on each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized as 226 8-bit words, commonly expressed as 64M×8. Memory manufactured in this way is low-density RAM and is usually compatible with any motherboard specifying PC3200 DDR-400 memory.

Mobile DDR
MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. Through techniques including reduced voltage supply and advanced refresh options, Mobile DDR can achieve greater power efficiency.

Source: 1

In Case You Missed Previous Threads:
Chapter 70: All About Fiber Optics
Chapter 69: All About S/PDIF

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Grandmaster Bunny

Solver13 | from Redmi Note 4

#1

Beautifully explained!
2019-03-07 12:52:57

Techie Team

J C Paul | from Redmi Note 4

#2

Informative!! Thanks for sharing :)
2019-03-07 22:22:53

Master Bunny

51916535 | from Redmi 6A

#3

OMG! this is awesome, brilliant information. Thanks for sharing with us. Are you teacher and tuition teacher or what? Bro.
2019-03-09 12:16:10

Pro Bunny

5177248287 | from Redmi Y2

#4

Thanks for sharing
2019-03-22 02:58:02

Advanced Bunny

P13r_ | from Redmi Note 5

#5

WOW! SO COOL!
2019-03-22 03:31:00

Master Bunny

Raza Haider | from Redmi 5A

#6

Well explained.
2019-03-22 03:47:05
Raza Haider

Semi Pro Bunny

deen mohamed | from Redmi Note 5

#7

good information...
2019-03-22 04:10:20

Rookie Bunny

PRASAD89 | from app

#8

Nice explained.
2019-03-22 04:18:29

MIUI Beta Tester

Asha@63. | from app

#9

Good Explanation
2019-03-22 04:26:04

Resource Team

iamumesh | from Redmi Note 5 Pro

#10

Well explained!
2019-03-22 04:47:52
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